Method and apparatus for scheduler coupled to memory array wherein scheduler addresses array with at least a portion of an identification number

ABSTRACT

Briefly, in accordance with one embodiment of the invention, an apparatus includes an integrated circuit that has the capability to schedule transferring processes that have an individual identification number. At least a portion of each individual identification number is used to indicate the presence of each of the transfer processes. Briefly, in accordance with another embodiment of the invention, an integrated circuit having a scheduler of transfer processes, each of the transfer processes having an identification number. The scheduler is coupled to a memory array of bits, and a portion of each identification number is used as a portion of an address to the memory array of bits. Briefly, in accordance with yet another embodiment of the invention, a method of scheduling requests for the transfer of data where each request having an identification number. The identification number is used in addressing a bit in an array of bits and set to indicate the request for the transfer of data.

BACKGROUND

This invention relates, in general, to computing networks, and moreparticularly, to scheduling the flow of information through a network.

As technology advances, the complexity and number of devices that areconnected to computing or communication networks increases. This in turnincreases the amount of information that is shared between the devicesvia the network. To reduce the number of connections employed, it isdesirable to design the network so that the devices may share many ofthe same interconnect wires. By reducing the number of wires, thereliability and efficiency of the network is improved and the overallcost of the network is reduced.

To allow multiple devices to share the same connections, networks mayinclude a scheduler to schedule the flow of information across thenetwork. Various protocol mechanisms may be used by the scheduler todetermine which device in the network is allowed to use a connection.This determination may be based in whole or part on the priority eachdevice is given by the network. Conventionally, a scheduler may use around-robin system to allow each device to have its turn sending orreceiving information across the network. However, the use of around-robin approach may be difficult to implement and inefficient giventhe priorities of a particular set of devices.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter regarded as the invention is particularly pointed outand distinctly claimed in the concluding portion of the specification.The invention, however, both as to organization and method of operation,together with objects, features, and advantages thereof, may best beunderstood by reference to the following detailed description when readwith the accompanying drawings in which:

FIG. 1 is a block diagram representation of a portion of a system havinga scheduler in accordance with an embodiment of the present invention;

FIG. 2 is a block representation of a memory array of bits in accordancewith an embodiment of the present invention; and

FIG. 3 is an illustration of an identification number that may be usedin accordance with various embodiments of the present invention.

It will be appreciated that for simplicity and clarity of illustration,elements illustrated in the figures have not necessarily been drawn toscale. For example, the dimensions of some of the elements areexaggerated relative to other elements for clarity. Further, whereconsidered appropriate, reference numerals have been repeated among thefigures to indicate corresponding or analogous elements.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are setforth in order to provide a thorough understanding of the invention.However, it will be understood by those skilled in the art that thepresent invention may be practiced without these specific details. Inother instances, well-known methods, procedures, components and circuitshave not been described in detail so as not to obscure the presentinvention.

Some portions of the detailed description which follow are presented interms of algorithms and symbolic representations of operations on databits or binary digital signals within a computer memory. Thesealgorithmic descriptions and representations are the techniques used bythose skilled in the data processing arts to convey the substance oftheir work to others skilled in the art. An algorithm is here, andgenerally, considered to be a self-consistent sequence of acts oroperations leading to a desired result. These include physicalmanipulations of physical quantities. Usually, though not necessarily,these quantities take the form of electrical or magnetic signals capableof being stored, transferred, combined, compared, and otherwisemanipulated.

It has proven convenient at times, principally for reasons of commonusage, to refer to these signals as bits, values, elements, symbols,characters, terms, numbers or the like. It should be understood,however, that all of these and similar terms are to be associated withthe appropriate physical quantities and are merely convenient labelsapplied to these quantities. Unless specifically stated otherwise, asapparent from the following discussions, it is appreciated thatthroughout the specification discussions utilizing terms such as“computing” or calculating” or “determining” or the like, refer to theaction of a computer or computing system, or similar electroniccomputing device, that manipulates and transforms data represented asphysical (electronic) quantities within the computing system's registersand/or memories into other data similarly represented as physicalquantities within the computing system's memories, registers or othersuch information storage, transmission or display devices.

FIG. 1 is a block diagram representation of a portion of a system 10 inaccordance with just one embodiment of the present invention. System 10represents a network comprising various devices 20-29 that are connectedtogether. However, it should be understood that the present inventionmay have application to not just macro-networks as shown in FIG. 1, butmay also be applicable to micro-networks. Examples of micro-networkswould include microcontrollers, microprocessors, integrated circuits,and the like, where information is exchanged between modules within themicro-network across a bus or similar communication path.

As illustrated in FIG. 1, system 10 may include an integrated circuit 20that is used to transfer data between devices 20-29. In this embodiment,integrated circuit 20 includes a scheduler 50 and Direct Memory Access(DMA) controllers 30 and 31. However, it should be understood thatintegrated circuit 20 may include other modules such as amicroprocessor, memory array, and the like. Furthermore, in alternativeembodiments of the present invention, system 10 and integrated circuit20 may be implemented using multiple integrated circuits.

Simply stated, scheduler 50 functions in cooperation with DMA's 30—31 tocontrol the flow of data transfers within system 10. Each of DMA's 30-31may have a number of ports 101-104 that are each connected to wires 1-4,respectively. However, it should be understood that the use of wires 1-4is only illustrative and it is not necessary that data transfers inaccordance with the present invention be limited to transfers over wire.

Ports 101-104 of DMA 30 are used to transfer data from devices 26-29 todevices 20-25. Similarly, DMA 31 is used to transfer data from devices20-25 to devices 26-29. Wires 1-4 are used, at least in part, totransfer data to and from devices 20-29, and the sequencing of the flowof data is determined by scheduler 50. Of course, the present inventionis not limited in scope to this particular configuration as the numberof ports and wires may be adjusted as the customer desires.

In this context, a transfer of data or signal information from onedevice to another is referred to as a transfer process. Although thepresent invention is not limited in scope in this respect, data may betransmitted and received throughout system 10 using the protocol definedin the Wekiva Architecture: Link Specification, version 0.9, dated Jul.15, 1999, available from Intel Corp., Santa Clara, Calif.

It should be understood that the present invention may also haveapplication in a variety of other system configurations. For example,devices 20-25 and 29 may be a variety of user or system components thatare coupled to system 10. For example, devices 20-25 and 29 may comprisewithout limitation printers, monitors, disk drives, scanners, memorystorage units, microprocessors, microcontrollers, caches, storage farms,fabric managers, switches, routers, application software, systemsoftware, any input/output (I/O) device, or the like.

In addition, as shown in the embodiment illustrated in FIG. 1, system 10may include specific devices such as a microprocessor 26, a memorydevice 27, or a bus 28 in communication with another network. However,it should be understood that it is not necessary for system 10 to haveall or any of these devices 20-29 in order to appreciate the benefits ofthis embodiment of the present invention. It is possible for system 10to have just one of devices 20-29 or a few, or other devices.

In this particular embodiment of the present invention, a request totransfer data may begin with devices 20-29 creating an identificationnumber that contains signal information related to the type and originof the request. FIG. 2 is an example of a transfer processidentification number 200 that may be used in accordance with thisembodiment of the present invention. It should be understood by thoseskilled in the art that the transfer process identification number mayalso be referred to as a virtual interface (VI) number or simply an IDnumber.

If a device 20-29 needs to transfers data, it generates anidentification number 200 that provides, in this embodiment, theidentity of the device, the priority of the request, and the port to beused for the transfer. Of course, other information may be included.These various portions are illustrated in FIG. 2. It should beunderstood that the scope of the present invention is not limited tothis embodiment and it is not necessary that the identification numberinclude all of this information. For example, an embodiment of thepresent invention may be used in a system that does not have a prioritysystem or only has one port for communication. In such applications, theidentification number may only designate the device making the transferrequest, although this is just one example.

Since multiple devices within system 10 may have a request to transferdata (e.g., a transfer process), scheduler 50 determines which device ispermitted to use DMA's 30-31 in order to prevent multiple devices fromcommunicating at substantially the same time. To do this, a memory array51, in this embodiment, is used to record when a device has generated aprocess to transfer data. Memory array 51 comprises an array of bitsarranged in rows and columns that may be located either within scheduler50 or externally to scheduler 50 and integrated circuit 20. Furthermore,memory array 51 may be implemented in a variety of ways including, butnot limited to, as a static random access memory (SRAM), as a dynamicrandom access memory (DRAM), as a non-volatile memory, as a disk drive,or the like.

When scheduler 50 receives a transfer process request having anindividual identification number, all or a portion of the digital valuesof the individual identification number are used to address memory array51. Thus, a portion of the transfer process identification number isused to address each bit in memory array 51. In this embodiment, eachlocation in memory array 51 comprises a bit that that is set to indicatewhen scheduler 50 has received a transfer process request with thatparticular identification number. Devices 20-29 generate a uniqueidentification number. The bit within memory array 51 may be used torepresent the request for a transfer process.

For example, if system 10 is capable of handling 64K identificationnumbers, then memory array 51 comprises 64K bits that indicate when atransfer process having each individual identification number has beenreceived by scheduler 50. The actual configuration of rows and columnsmay be varied to improve the efficiency and speed of scheduler 50. Oneexample of how memory array 51 may be arranged is illustrated in FIG. 3.As shown, memory array 51 may comprise 2K rows with each row having 32columns. Thus, if the identification number of each transfer processcomprises 16 bits, then eleven (11) of the bits may be used to determinewhich row is selected and five (5) bits may be used to determine thecolumn within the row. Of course, the scope of the present invention isin no way limited to this particular configuration. In general, if theidentification number contains N bits, then memory array 51 may compriseat least 2^(X) rows and 2^((N-x)) columns. It should also be understoodthat in alternative embodiments, it is not necessary that each transferprocess number have a designated location in memory array 51 and thenumber of memory locations within memory array 51 can be greater than,equal to, or less than the number of possible transfer process numbers.

Once the appropriate bit or bits within memory array 51 have been set toindicate the presence of transfer process requests of the devices 20-29within system 10, scheduler 50 determines which of the requests is giventhe next opportunity to communicate. One method of determining the nextrequest would be to begin searching each location of memory array 51until a bit that has been set is found. However, this may not be themost efficient technique if memory array 51 is relatively large andincludes few transfer process requests because a lot of time may bewasted polling bits that do not indicate the presence of a transferprocess request.

To address this problem, the searching of memory array 51 for processesmay be expedited with the use of flags. A flag may be set to indicatethat at least one of the bits contained within a sub-portion of memoryarray 51 has been set. In the embodiment shown in FIG. 3, a flag(labeled Flag0-Flag2047) is used to indicate if any of the bits in thatparticular row, (e.g., rows 0-2047, respectively) have been set. Ifscheduler 50 has not received a transfer process request correspondingto the bit locations of a given row, then the flag for that row will notbe set to indicate that there is no need to search that particular rowfor transfer process requests. Such an arrangement may provide for abinomial search of memory array 51.

It may also be desirable to use additional levels of flags thatpartition memory array 51 into larger sections to further expedite thesearching of memory array 51. As shown in FIG. 3, a second set of flags(labeled 2Flag0-2Flag511) may be employed where each of the second setof flags is used to indicate if any of the first set of flags(Flag0-Flag2047) has been set. For example, the second set of flags mayindicate if one of four rows of memory array 51 has a bit that has beenset. For example, 2Flag0 is set if any of flags Flag0-Flag3 have beenset and so on. The use of multiple levels of flags provides forpolynomial searching of memory array 51. However, it should beunderstood that the use of any flags or multiple levels of flags is notnecessary for an embodiment of a system to fall within scope of thepresent invention.

In the embodiment illustrated in FIG. 1, only a portion of theidentification number is used by scheduler 50 to determine thesequencing of transfer process requests from devices 20-29.Consequently, additional schedulers may be desired to control the flowof transfer process requests for the ports of system 10 and for thepriority levels used within system 10. Thus, in alternative embodimentsof the present invention, the system may have multiple schedulersdedicated for each port and priority. Alternatively, one scheduler maybe multiplexed. In addition, it may be desirable to use all or a portionof the port and priority bits of the identification number 200 (see FIG.2) to address memory array 51.

By now it should be appreciated that one embodiment of the presentinvention provides a system having a scheduler that may be used tocontrol, at least in part, data transfers between devices. By using allor a portion of the identification number of a transfer process requestto map a memory array, the need to maintain a FIFO system to determinethe next transfer to be processed has been obviated. Furthermore, anembodiment of the present invention may include the use of flags tofurther improve the efficiency of the scheduler in determining the nexttransfer to be performed. Such improvements may increase the efficiencyof the network and reduce its cost as well.

While certain features of the invention have been illustrated anddescribed herein, many modifications, substitutions, changes, andequivalents will now occur to those skilled in the art. It is,therefore, to be understood that the appended claims are intended tocover all such modifications and changes as fall within the true spiritof the invention.

What is claimed is:
 1. An apparatus comprising: at least one integratedcircuit; the integrated circuit including the capability, either aloneor in combination with other integrated circuits, to scheduletransferring of a plurality of transfer processes, at least some of theplurality of transfer processes having an individual identificationnumber, wherein the integrated circuit is adapted to use at least aportion of an individual identification number directly as at least partof an address to an array of bits to indicate the presence of at leastone of the plurality of transfer processes.
 2. The apparatus of claim 1,wherein each individual identification number comprises at least N bits,and the array of bits comprises at least 2^(x) rows and 2^((N-x))columns.
 3. The apparatus of claim 2, wherein N is
 16. 4. The apparatusof claim 3, where in x is
 5. 5. The apparatus of claim 2, and furthercomprising a first set of flags, wherein each of the first set of flagsis capable of indicating if a portion of the array of bits indicates thepresence one of the plurality of transfer processes.
 6. The apparatus ofclaim 5, and further comprising a second set of flags, wherein each ofthe second set of flags is capable of indicating if a sub-set of thefirst set of flags indicates the presence of a portion of the pluralityof processes.
 7. The apparatus of claim 6, wherein the first set offlags and the second set of flags are capable of providing a polynomialsearch of the array of bits.
 8. The apparatus of claim 1, wherein theapparatus is a computing network including at least a first device and asecond device, and each of the plurality of transfer processesrepresents a request from the first device for a transfer of data to thesecond device.
 9. The apparatus of claim 8, wherein the first device isselected from the group consisting of a memory storage unit, a printer,a microprocessor, a microcontroller, a monitor, and a cache.
 10. Anintegrated circuit comprising a scheduler of transfer processes, each ofthe transfer processes having an identification number, wherein thescheduler is coupled to an array of bits, and wherein at least a portionof each identification number is directly used as at least a portion ofan address to the memory array of bits.
 11. The integrated circuit ofclaim 10, wherein each of the bits in the array of bits is capable ofindicating the presence of a transfer process.
 12. The integratedcircuit of claim 10, and further comprising a first set of flags forindicating if a sub-portion of the memory array of bits indicates thepresence of a transfer process.
 13. The integrated circuit of claim 12,wherein the first set of flags is capable of providing a binomial searchof the memory array of bits.
 14. The integrated circuit of claim 12, andfurther comprising a second set of flags for indicating if a sub-portionof the first set of flags indicates the presence of a transfer processin a sub-portion of the memory array of bits.
 15. The Integrated circuitof claim 14, wherein the first set of flags and the second set of flagsare capable of providing a polynomial search of the memory array ofbits.
 16. The integrated circuit of claim 10, wherein eachidentification number comprises at least N bits and the memory array ofbits comprises at least 2^(x) rows and 2^((N-x)) columns.
 17. A systemcomprising: a scheduler; the scheduler being adapted to determinepriority for a plurality of transfer processes with an identificationnumber associated with at least some of the plurality of transferprocesses, wherein the scheduler is adapted to use at least a portion ofthe identification number to directly address a bit in an array of bits.18. The system of claim 1, wherein each bit in the array of bits isadapted to indicate the presence of a transfer process.
 19. The systemof claim 18, and further comprising a first device and a second device,wherein each transfer process represents a request to transfer data fromthe first device to the second device.
 20. A system comprising: ascheduler that determines priority for a transfer process, the transferprocess represented by an identification number; and a memory arraycoupled to the scheduler, wherein the scheduler is capable of addressingthe memory array with at least a portion of the identification number.21. The system of claim 20, and further comprising a plurality ofdevices and a plurality of ports for directing the flow of the transferprocess between the plurality of devices, and wherein the identificationnumber has a first portion adapted to indicate which of the plurality ofdevices originated the transfer process and a second portion that isadapted to indicate which of the plurality of ports is to be used forthe transfer process.
 22. The system of claim 21, wherein theidentification number has a third portion adapted to indicate thepriority of the transfer process.
 23. The system of claim 22, andfurther comprising a plurality of schedulers adapted to determinepriority for each of the plurality of ports.